Visibl Semiconductors: AI-Native Broadcom as a Service

AI-Native Broadcom as a Service

Visibl is an AI platform that turns compute into chip design capacity. As chips grow more complex, adding engineers yields diminishing returns — coordination costs rise while progress slows. The bottleneck is no longer ideas, but execution throughput. Visibl turns compute into a teammate. Our platform ingests the full design context (code, specs, scripts, tool outputs) to decode ambiguous tool feedback into actionable steps. We validate changes and package decisions for review, resulting in safer changes, shorter iteration cycles, and fewer late surprises on the path to tapeout.

Active Founders

Bryce Neil

Founder

Co-founder & CEO at Visibl Semiconductors. Lifelong hacker and recipient of two of Canada’s most competitive academic scholarships. Bryce is a computer engineer with experience across engineering, data, and business. He has built production software and data systems for Deloitte’s OmniaAI team, healthcare, and the public sector. His work has run in leading U.S. hospitals and supported teams globally.

Bryce Neil

Founder

Co-founder & CEO at Visibl Semiconductors. Lifelong hacker and recipient of two of Canada’s most competitive academic scholarships. Bryce is a computer engineer with experience across engineering, data, and business. He has built production software and data systems for Deloitte’s OmniaAI team, healthcare, and the public sector. His work has run in leading U.S. hospitals and supported teams globally.

Jordon Kashanchi

Founder

Co-founder & CTO of Visibl Semiconductors. Jordon previously worked at Microsoft, Arm, and Intel, building expertise in AI accelerators, autonomous vehicle hardware, and graphics. Most recently at Microsoft, he designed digital logic and microarchitecture for next-gen custom AI silicon. He holds an MS in ECE from UT Austin and is published in PNAS and ACM.

Jordon Kashanchi

Founder

Co-founder & CTO of Visibl Semiconductors. Jordon previously worked at Microsoft, Arm, and Intel, building expertise in AI accelerators, autonomous vehicle hardware, and graphics. Most recently at Microsoft, he designed digital logic and microarchitecture for next-gen custom AI silicon. He holds an MS in ECE from UT Austin and is published in PNAS and ACM.

Company Launches

Visibl Semiconductors: The First AI-Enabled Coordination Layer for Chip Design

See original launch post

Hey everyone 👋
We’re Bryce and Jordon, co-founders of VISIBL SEMICONDUCTORS™

Launch video: https://youtu.be/l_0BcKIIU3Q

TL;DR
Visibl is the first coordination layer for chip design. Requirements, architectural intent, and implementation drift out of sync as designs and teams scale. Visibl surfaces drift early, opens cases with evidence, and delivers review-ready fixes enabling improved schedule, cost, and risk outcomes in chip design.

Check out LinkedIn post here:
https://www.linkedin.com/posts/y-combinator_visibl-semiconductors-yc-w26-is-building-activity-7430280268252590081-UBoI/

Problem
Coordination has always been a human job: monitoring drift, triaging failures, keeping the schedule aligned. It demands constant vigilance, reacting to failures, proactively scanning for issues, always watching.

As designs scale, no one can hold all that context: the specs, the implementation, the test results, the decisions scattered across Slack, Jira, and docs. Issues slip through. Drift compounds. We saw this firsthand. There was no software to solve it. So we're building it.

Our experience spans chip design and high-stakes production systems. We're solving a problem there was never enough human bandwidth to address, but one that directly impacts the most important outcomes in chip design: schedule, cost, and risk.

What Visibl Does

Monitors - specs, implementation, CI, and all design collateral to detect drift early

Investigates - creates cases with evidence: spec sections, RTL refs, CI logs, historical decisions

Proposes - agents suggest fixes, run verification, package review-ready diffs

Gates - human approval required, nothing ships without explicit sign-off

—

Results

Schedule - Eliminate weeks lost waiting for the one engineer with context to debug failures

Cost - 10x less engineering overhead on triage; your team builds instead of firefighting

Risk - Catch issues early to minimize rework; avoid late-stage surprises that lead to $10M+ respins

Instant Dispatch & Case Creation

uploaded image

Agents spin up immediately on regressions, failing PR checks, spec updates, and more. Visibl opens a case automatically.

—

Evidence Bundle

uploaded image

Each case comes preloaded with spec sections, RTL refs, CI logs, and decision history.

—

Recommended Fix

uploaded image

Visibl proposes three fix paths and recommends the best one for approval. User can also clarify and specify their own intent.

—

Verified Review-Ready Diff

uploaded image

Approved changes are applied, verified, and packaged as a review-ready diff with results.

Role-Based, Team-Based, and Individual Views

uploaded image

Role-specific views surface the same underlying truth at the right level of detail. For example, the executive view shows how Visibl ambiently ingests signals across the org and distills them into what leaders care about most—readiness, schedule impact, and top tapeout risks—so they can take action quickly. Visibl also lets executives (and every role) act directly on these insights, drill into the underlying evidence, assign owners, and drive cases to resolution.

Our Ask

If you have a friend who designs chips at a semiconductor or hardware company, we would really appreciate an intro. Even a quick forward of this post helps.

If you are a:

DV / CI owner
Design methodology / flow owner
Team heading into integration, freeze, or pre-tapeout

…we’d love to talk.

Schedule a demo: founders@visiblsemi.com