Partcl

Imagine hitting compile and waiting 3 weeks to learn you missed a semicolon... or 5 weeks to catch a runtime error.

Welcome to ASIC life.

We're slashing those weeks down to minutes — so you can build better chips, faster.

🤔 Why did we build this?

During our time at Nvidia and other startups, we found that engineers spend large amounts of the 24 month chip design cycle idle, waiting for runs to finish.

Partcl speeds up Physical Design tools by rearchitecting algorithms for GPUs.

🧑‍💻What it means for designers:

• Quick power, performance, and area estimates
• Fix timing/power bugs in RTL w/out handoff to the PD team
• Build better chips, faster

✅What we have right now:

• 700X faster Static Timing Analysis - enabling super quick performance simulations
• 100X faster Gate Resizing
• 100X faster global and detailed placement

🔜What’s in the pipeline:

• LSP integration for Incremental synthesis - Synthesis as fast as you can type
• Natural Language interface to any intermediate database - Directly query the state of your database with text instead of asking a junior engineer to build you a dashboard

Our Ask

Email us at {vamshi, will}@partcl.com to try Partcl and let us know what you think.

Are you building

• AI Accelerators? Partcl brings in tapeout deadlines with faster tools, bringing your chip to market faster!
• Embedded/ IoT devices? Partcl decreases NRE by shrinking design cycles. Decreased NRE directly translates to higher margins.
• Mobile SoCs? Partcl’s physics informed models let you optimize the power-performance tradeoff for your use case.