The co-pilot for chip designers
We're looking for an experienced chip designer with a strong full-stack software + ML skillset to build the co-pilot for chip designers with us. You will be pushing and productizing the frontier of EDA tools & ML techniques to enable our novel use cases.
As our Founding R&D Engineer, you will be working directly with our CTO to co-own, architect, and ship co-pilot software enabling functional correctness convergence and PPA optimization in RTL design. You will also be working directly with our world-class customers building advanced chips and IP to understand their needs and iterate on our product with real feedback.
Apply to chat with us about the role in more detail!
Note that this is an in-person role in the SF Bay Area.
Silimate is the co-pilot for chip designers.
Chip teams today are still using the same archaic workflows from 30 years ago, resulting in lengthy 12-18 month design cycles and the inability to ship chips fast enough to keep up with the software pointer.
We're changing that at Silimate.
Our chip design co-pilot is helping chip designers write correct, PPA-optimized RTL code from the onset, and build better chips in less time. We're building a catalytic tool for the chip industry.
We're well-funded by top investors and are generating revenue with customers that are world-class chip and IP design companies. We're growing fast — demand for Silimate has outpaced our ability to build and ship the product. We're looking for excellent engineers that are passionate about the semiconductor chip space to join us.