TL;DR: Silimate automates chip workflows with an intuitive end-to-end platform, so chip designers can focus all their time on their actual differentiating design work.
Hey everyone, we’re Ann and Akash, and we used to design chips! Now we’re on a mission to make semiconductor chip design faster and easier.
❌ The Problem
The chip design workflows today are:
- Unintuitive: Typically Makefiles, TCL scripts, and lots of tribal knowledge that’s difficult to scale.
- Fragmented: At every company, there’s tons of ad hoc scripts that reinvent the pieces of a silicon chip flow, which is time/$$ wasted.
- Primitive: Because of this fragmentation, teams often end up with relatively primitive implementations that are fragile and difficult to maintain/enhance.
The result? Chip designers spend 30-70% of their time (depending on where they are in the design cycle) debugging unintuitive flow errors, writing one-off scripts, or sifting through gigabytes of log files – instead of doing cool stuff like architecting experiments or building new hardware features.
✨ Our Solution
Silimate is an out-of-the-box silicon flow platform that puts the chip designer in the cockpit. The platform acts as a co-pilot, taking instructions and executing them on behalf of the pilot.
Silimate helps designers build, understand, and experiment:
- Build: Auto-build and run any part of their simulation/RTL2GDS flows with a toolbox that natively understands silicon dependencies
- Understand: Auto-parse and visualize the results of runs over time, correlating design changes to quality-of-results
- Experiment: Take user-defined parameter constraints and target metric outcomes, then run design-of-experiments to optimize
🌎 Why Now
Death of Moore’s Law, an explosion of custom chip architectures, geopolitics (CHIPS Act), talent shortage, massive demand for AI chips – we’re psyched to build the pickaxe for the silicon renaissance.
👋 Asks: how you can help
- We’re giving beta users access to our cloud environment with open-source EDA tools! If you’re a hobbyist chip designer, an academic silicon researcher, or an individual engineer at a chip company, fill out this form to sign up! We’d love your feedback.
- We’re deploying for our early enterprise customers. If your chip team is dealing with the pains of ad hoc flows, email us – we’d love to help.
- If you’re not a chip designer but know one (or a few), send them our way!
Follow along on our journey here!